Safi Aridi
I am a Computer Engineering student and researcher based in Beirut, Lebanon. My technical focus spans the entire computing continuum: from logic gates and instruction pipeline hazards on silicon, to embedded microcontroller firmware, software security, signal processing, and spatial GIS mapping.
At LAU Beirut and within the IEEE Student Branch, I actively build open-source engineering software, explore low-level systems architectures, and develop reproducible research tools for information hiding and geospatial analysis.
Lebanese American University (LAU Beirut)
Bachelor of Engineering in Computer Engineering (B.E.)
Lebanese American University · Beirut Campus, Lebanon
Tree structures, graph traversal, dynamic programming, and complexity proofs.
Pipelined datapath design, branch prediction, cache hierarchies, and memory models.
Kernel scheduling, concurrency primitives, virtual memory management, and file systems.
Combinational/sequential logic synthesis, finite state machines, and FPGA implementation.
Interrupt handling, DMA controllers, peripheral bus architectures, and RTOS.
Symmetric/asymmetric ciphers, cryptographic hash functions, and protocol vulnerability.
RLC circuit resonance, signal transmission lines, and precision photometric measurement.
IEEE Student Branch Involvement
Technical Workshop Leadership
Organizing hands-on sessions for students on microcontroller programming (STM32/ESP32), oscilloscope debugging, and circuit analysis fundamentals.
Hardware Hackathons & Projects
Collaborating on student engineering initiatives involving embedded sensor networks, real-time telemetry pipelines, and digital logic prototypes.
Security & Systems Seminars
Presenting research on video steganography mechanics, cryptographic verification techniques, and low-latency computer architecture design.
Laboratory & Systems Capabilities
Systems & Low-Level Languages
Memory management, bare-metal pointers, concurrency, bit-manipulation, and zero-copy data structures.
Hardware & Laboratory Tools
Digital logic synthesis, serial protocols (SPI, I2C, UART), sensor interfacing, and hardware-software co-design.
Security & Signal Processing
Information hiding, cryptographic payload verification, spectral decomposition, and noise filtering.
Spatial GIS & Web Architecture
Satellite radiance data processing, vector tile generation, high-contrast UI engineering, and web telemetry portals.
Engineering Resume & Verified Credentials
Curriculum Vitae // Safi Aridi
Verified academic credentials, laboratory research, and systems engineering history
Safi Aridi
Computer Engineering @ Lebanese American University (LAU Beirut) · IEEE Member
01. Academic Credentials
Lebanese American University (LAU Beirut)
Beirut, Lebanon- Core Coursework: Computer Architecture, Data Structures & Algorithms, Digital Systems Design, Microprocessors & Embedded Systems, Physics Laboratories, Operating Systems, Cryptography & Network Security, Discrete Mathematics.
- IEEE Student Branch Member: Active participant in student technical workshops, hackathons, and hardware design seminars.
02. Selected Engineering Research & Projects
Video Steganography Engine (Data Payload Embedding in Video Streams)
C++ / OpenCV / CryptographyEngineered a high-throughput video steganography framework embedding encrypted payloads into uncompressed and H.264 video streams via spatial LSB manipulation and discrete cosine transform (DCT) coefficient perturbation. Maintained PSNR > 51 dB with SHA-256 HMAC integrity verification.
Lebanon Dark-Sky GIS Observatory (Spatial Light Pollution Analysis)
GIS / Python / MapLibre / PostGISConstructed a geospatial analysis platform integrating VIIRS Day/Night Band satellite radiance data to map light pollution levels and Bortle classes across high-altitude Lebanese peaks (Qurnat as Sawda, Tannourine, Sannine, Chouf Biosphere).
Hardware & Signal Physics Suite (Resistor Decoders & Signal Synthesizer)
React / TypeScript / Digital LogicDesigned interactive computational engineering utilities for real-time IEC 60062 4-band/5-band resistor decoding, tolerance margin validation, and continuous-time Fourier harmonic synthesis for electronics prototyping.
5-Stage Pipelined RV32I Microprocessor Core
SystemVerilog / Xilinx Vivado / ModelSimSynthesized a 32-bit RISC-V processor core with full forwarding units, hazard detection logic, and branch stall resolution. Validated with benchmark assembly suites on FPGA hardware.